James Stanbridge, regional manager at JTAG Technologies, explains how design tools and automatic boundary-scan (aka JTAG) test program generators can interface at a range of advanced levels.
Many engineers are now working with a host of automation tools that cover wide-ranging tasks such as FPGA design schematic entry, layout and increasingly board test development. As the trend continues towards smaller design teams, hardware engineers are looking more closely at ways to improve efficiency and speed time to market – in spite of increasing workloads. One way in which efficiency improvements can be made is by forging stronger links between EDAs and PCB test development toolsets.
Schematic entry (drawing) systems are used to draw circuits and also to create an interconnection table (netlist) that can be used by down-stream tools such as board layout systems and manufacturing and test tools. Boundary-scan test systems such as JTAG Technologies’ ProVision allow the import of many different netlist types, principally from schematics but also from down-stream systems such as board layout or CAM (Computer Aided Manufacturing) tools.
By analysing connectivity datain conjunction with component models (including the BSDL* test description models) it is possible to get an early indicator of fault coverage using JTAG/Boundary-scan. JTAG ProVision software for example includes a fault coverage analyser that provides two outputs listing a) predicted and b) actual fault coverage – depending on how far through the (test) development cycle you wish to go.
The predicated coverage for example is derived from only the basic raw inputs (Netlist(s), device models and BSDLs) and makes assumptions regarding I/O access to connectors and test-points. Actual coverage on the other hand is derived following an analysis of all PCB tests that have been created.
Importing full EDA data including component symbols into test tools offers a number of further advantages for the engineer responsible for PCB test. Professional-level test tools that can support a schematic viewer ‘plug-in’ module are able to overlay fault coverage data on to the schematics. By highlighting fault coverage differences using a colour coding system it is easy to get an ‘at a glance view’ of the PCB sectors that are being fully tested and those that may require further attention. The screenshot in figure 1 shows a PCB with 100% (all nodes) test coverage highlighted in white for example. Engineers then have the ability to set guarding values (fixed drive and sense points) on a circuit node from a schematic view which offers considerable benefits.
Interacting with board layouts
In addition to schematic views modern test tools can often also import board layout information in numerous formats, from the now ubiquitous ODB++ to proprietary formats from EDA tool vendors such as Cadence, Mentor, Zuken and Altium. In the boundary-scan domain, PCB tests that fail and are subsequently diagnosed as a net-level or pin-level fault, can be linked into the layout view and highlighted or zoomed-to (see figure 2). Individual layers can be stripped off as required and the PCB can even be viewed ‘flipped’ or from the underside to aid speedy diagnosis. What’s more fault analysis data can once again be overlaid onto the layout view.
Since its inception JTAG/boundary-scan has principally been associated with board-level testing. More recently however, JTAG test tool vendors have also seized upon additional features embedded within devices (ICs) that were not initially envisaged for testing. In microprocessors for example, the JTAG interface is often used to access not only the boundary-scan test register, but also internal registers included to exercise onchip debug (OCD) modes. Given access to the OCD features, engineers responsible for test can create more sophisticated tests using many more of the modules embedded within the microcontroller. A further example of the way in which design and test tools/technologies are now merging is in the use of JTAG access within the core of an FPGA. Most FPGA vendors now provide a resource (eg ‘megafunction’) that provides a bridge between the standard JTAG (IEEE 1149.1) TAP and the gate array fabric. Thus with some experience of the vendor design tools (Altera’s Quartus or Xilinx’s ISE for example) engineers responsible for test can construct specific test IP that can be triggered via the JTAG port.
In February 2013 JTAG Technologies extended this methodology by introducing a generic translator block that links the vendors JTAG <=> fabric bridge to standard embedded busses such as Wishbone, AMBA, Avalon and CoreConnect. In this way engineers can utilise standard IP blocks (e.g. DDR controllers, E-net MAC, CAN bus interfaces etc.) for test purposes by linking them back to the JTAG port.
In conclusion it is commonly found in smaller design teams and SMEs that the engineer responsible for test is also the hardware designer. In these circumstances it is not uncommon for this person to wish to ‘leverage’ their design skills and efforts for manufacturing test purposes. Test tool companies are now responding to this requirement and are providing many more features that allow the transfer of data and IP from design to test.
*BSDL = Boundary-Scan Description Language, a format that describes the test logic in ICs – see also IEEE Std 1149.1b