Synopsys has collaborated with TSMC to provide support for voltage-dependent design rules in TSMC’s 16nm Custom Design Reference Flow. As part of the company’s custom design infrastructure, TSMC has also certified Synopsys’ Laker custom design solution and circuit simulation tools for TSMC V0.5 16nm FinFET process layout design rules, device models, and electromigration and IR-drop (EM/IR) analysis. The two companies will continue to collaborate on certification of the Synopsys tool set until 16nm FinFET reaches V1.0.
Synopsys’ HSPICE circuit simulation, Laker custom layout and IC Validator physical implementation tools are used for voltage-dependent design rule checking. The company advises, VDRC rules require larger spacing between signals that have a high potential voltage difference. For VDRC validation, voltage ranges are calculated for each net by the circuit simulation tool, annotated onto the layout by the Laker layout editor, and then verified using IC Validator signoff verification.
Enhancements to the Laker tool for 16nm layout include new features for FinFET devices, including fin grid pattern snapping, fin display and interactive FinFET rule checking. A built-in double-pattern checking has been enhanced to support pre-colouring and colour density checking. Whilst support for middle end-of-line (MEOL) layers includes contactless connectivity, unidirectional layer rules and enhancements to support 16nm guard rings.
Synopsys advises it has enhanced the FinFET model used in HSPICE, CustomSim and FineSim for better performance, reduced memory footprint and enhanced multi-threading scalability. The TSMC Modelling Interface (TMI2.0) jointly developed by TSMC and Synopsys enables more accurate layout-dependent effect modelling on top of standard SPICE models.
TMI2.0 is also said to provide a unified infrastructure for statistical modelling, and MOS ageing simulation.
Synopsys has collaborated with TSMC to provide full signoff-accurate runsets for design rule checking (DRC) and layout-vs.-schematic (LVS) checks with TSMC 16nm V0.5. IC Validator is also integrated into the Laker user environment to allow running DRC and LVS signoff checks and for debugging layout errors with IC Validator’s VUE utility.
Low power design techniques in 16nm designs require accurate, simulation-based EM/IR analyses. Through close collaboration with TMSC, Synopsys has enhanced its CustomSim EM/IR analysis capability to comply with the new rules for 16nm designs and support TSMC’s iRCX format.
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