A New range of Advanced Low-Power SRAM (Advanced LP SRAM) Products has been released by Renesas Electronics that are claimed to offer improved reliability for manufacturers’ systems.
There are a total of twelve new product versions in the company’s RMLV0416E, RMLV0414E, and RMLV0408E series. These devices have a density of 4 megabits (Mb) and use a fine fabrication process technology with a circuit linewidth of 110 nanometers (nm).
A 150nm process has been used, including soft error free and latch-up free. They also achieve low-power operation with a standby current of maximum of 2microamperes (µA) at 25°C, making them suitable for data storage in battery-backup devices.
The company advises, SRAM is becoming an important factor in improving overall system reliability. In particular, SRAM used to store important information such as system programs and billing data must provide a high level of reliability; and particular measures must be focused on reducing soft error caused by alpha radiation and cosmic neutron radiation.
In response, it has developed its Advanced LP SRAM structure in which each memory node within the memory cells has an added physical capacitor capable of delivering high endurance against soft error. The company advices, a general method of dealing with soft error after they occur is the inclusion of an internal error correcting code (ECC) circuit in the SRAM or the manufacturer systems.
This approach has its limits, however, and there may be cases where the performance of the ECC is unable to deal with errors affecting multiple bits. In contrast, these devices use structural measures to prevent the soft error themselves from occurring.
Results from the evaluation of system soft error in 150nm Advanced LP SRAMs that are currently in mass production prove that, in practical terms, these products can be called soft error free.
Also, the SRAM cell load transistors (P-channels) are polysilicon TFTs and they are stacked on top of the N-channel MOS transistors on the silicon substrate. Therefore, only the N-channel transistors are formed below on the silicon substrate. This ensures that no parasitic thyristors can form within the memory area and theoretically makes latchups impossible. 
Renesas Electronics Europe
