Enabling early RTL exploration
Chris Allsup, Marketing Manager for Synopsys’ Synthesis and Test Group, explores how Register Transfer Level code is leading to faster implementation. The register transfer level (RTL) code for today’…
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Next generation virtual machine technology
18 Dec 2011 | EDA
Next generation embedded Virtual Machine technology has been released by Atego. The Aonix Perc Ultra 6 introduces support for Java 6 language for the first time and incorporates a new high-…
Read MoreAdvance in differential memory signalling
18 Dec 2011 | EDA
Advanced differential signaling for SoC-to-memory interfaces has been developed by Rambus Inc. The SoC has a 20 gigabits per second (Gbps) and can extend single-ended memory signaling to 12.8Gbps. …
Read MoreDesign & test for 3G/4G and LTE-advanced
18 Dec 2011 | EDA
A communications test and measurement solution for 3GPP LTE-Advanced, LTE,W-CDMA, HSPA+, E-EDGE (EDGE Evolution), has been developed by Agilent Technologies Inc. The commercial design support for the …
Read MoreHierarchical reference flow for Common Platform
18 Dec 2011 | EDA
A hierarchical RTL-to-GDSII reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology has been released by Magma Design Automation. The tool utilises the …
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