Advanced differential signaling for SoC-to-memory interfaces has been developed by Rambus Inc. The SoC has a 20 ­gigabits per second (Gbps) and can extend single-ended memory signaling to 12.8Gbps. The company has also ­developed technology that enables a seamless transition for memory architectures from single-ended to differential signaling; as data rates rise to meet the performance requirements of future-generation graphics and gaming systems.

The latest technology advancements of the company’s Terabyte Bandwidth Initiative enable power efficiency and compatibility to ­single-ended memory architectures, including GDDR5 and DDR3. With the addition of its FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. The company has achieved a power efficiency of 6 milliwatts (mW) per Gbps when operating at 20Gbps in a 40nm-process silicon test vehicle. These innovations address critical system ­challenges to extend signaling rates by addressing power efficiency and compatibility needs.