Xilinx has now taped out, what the company is claiming is the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. The company has also inaugurated the first ASIC-class programmable architectures called UltraScale. The company advises this is its first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite.  

 “When you combine TSMC’s technology, our UltraScale architecture, and co-optimisation with our Vivado Design Suite, we believe we are about a year ahead in delivering 1.5–2X more realiseable system-level performance and integration.”

Xilinx has now moved from 28nm to 20nm, resulting in what the company is claiming is the industry’s first tape-out of the first ASIC-class programmable architecture: UltraScale.

The UltraScale architecture was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through 3D ICs. It not only addresses the limitations to scalability of total system throughput and latency, but directly attacks the number one bottleneck to chip performance at advanced nodes: the interconnect. 

The company advises, an innovative architectural approach is required to manage multi-hundred gigabit-per-second levels of system performance with smart processing at full line rate, scaling to terabits and teraflops. The mandate is not simply to increase the performance of each transistor or system block, or scale the number of blocks in the system, but to fundamentally improve the communication, clocking, critical paths, and interconnect to address the massive data flow and real-time packet, DSP, and/or image processing.

The UltraScale architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture:

•Massive data flow optimized for wide buses that support multi-terabit throughput

•Multi-region ASIC-like clocking, power management, and next generation security

•Highly optimised critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing

•Step function in inter-die bandwidth for 2nd generation 3D IC systems integration

•Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface

•Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance

The initial UltraScale devices will extend the company’s Virtex and Kintex FPGA and 3D IC families now based on 28nm process technology, and will serve as the foundation for future Zynq UltraScale All Programmable SoCs. They will enable next generation smarter systems with new high-performance architectural requirements, including:

400G OTN with intelligent packet processing and traffic management

4X4 Mixed Mode LTE and WCDMA Radio with smart beamforming

4K2K and 8K displays with smart image enhancement and recognition

Highest performance systems for intelligence surveillance and reconnaissance (ISR)

High performance computing applications for the data centre

Xilinx

www.xilinx.com