For SoC product developers, worrying about the impact of memory power consumption is often way down the list of care-abouts. Indeed, it is enough of a challenge just juggling the demands of meeting feature, performance, area and system power goals. Typically, as memory IP is often sourced from the foundry or one of the big IP vendors then the power that they quote is the power you get; end of discussion. However, given that on-chip memory can now account for more than 50 percent of chip area and a significant chunk of the overall power budget too, then maybe it is time this critical element got bumped up that list.
The trend to use ever more advanced nodes continues unabated across the semiconductor industry in order to deliver more features at lower cost and power. However, for most off-the-shelf memory IP, the design optimisation criteria were often driven by the needs of the High Performance Compute or Mobile sectors delivering performance at the cost of power. Even for AI chip designers where performance is critical, standard memory solutions can mean eye watering power demands as more and more data needs to be transferred to and from the processor.
This is a growing problem in a wide range of applications with the most obvious being wearables, where there is a limited amount of battery power, and yet to remain competitive, developers need to add ever more functionality. This inevitably requires increased performance and hence ever greater power demand. This can be ameliorated to an extent by targeting a smaller node but as memory does not follow the same scaling rules as logic then cuts in memory power are often disappointing. For example, sureCore was able to significantly reduce the power demand for a chip used in a next generation hearing aid by designing a custom, ultra-low voltage memory solution. This enabled the machine learning-based, dynamic noise cancellation engine to deliver unparalleled clarity for users whilst still delivering a competitive battery life. Now in production, this product will significantly enhance the quality of life for its users.
Other applications are experiencing this power consumption issue, not from a battery life perspective, but because of thermal considerations. A key example is, of course, a data centre; hit by the double whammy of both high-performance compute power demands coupled with ever increasing cooling requirements. This problem, albeit at a smaller scale, is also impacting some automotive applications. One novel way of addressing this, for datacentres at least, is to cool the servers using low-cost liquid nitrogen to around 77K. Although this increases cooling costs by a factor of 3, this is more than made up for by the 7x reduction in compute energy needs, giving an overall saving of 4x. Of course, operating silicon at 77K (-196C) is somewhat outside the standard semiconductor operating range so more work is need to fully exploit this approach. Similarly in this space, sureCore’s cryogenic design expertise has been shown to deliver low power memory solutions operating at 4K and below.
Memory developers have historically focused on optimising either performance or area; with the underlying memory architecture remaining largely unchanged. From the outset, sureCore realised that to address the growing need to cut power consumption then a different approach was needed. For many applications, it makes sense to sacrifice some areas and, very often, for power sensitive designs then pushing the performance envelope is not a necessity. For the sureCore engineering team, this meant a return to first principles investigating and evaluating novel techniques and exploiting ultra-low voltage design methods to aid developers in their quest for the lowest power possible.
The SoC architect’s decision often boils down to either using standard memory IP, which is usually free but power hungry, or, if that approach will not meet the power budget, to use sureCore to provide memory IP that will meet the power budget and, potentially, result in a slightly bigger chip. As the power demands of just the on-chip memory can be in the region of 50 percent of the chips’ power budget, sureCore’s ability to cut this dramatically means that a bespoke memory solution can often be the only way to meet the power budget for a product and make it viable.
Bespoke memory solutions have been sureCore’s speciality for over a decade and with over a dozen patents to its name plus the accumulated low power design know-how, and expertise down to 6nm, the company is in an enviable position to address this challenge. SureCore meets with its customers to determine the exact power, performance and area requirements of the application to find the optimal architecture. This could be a custom designed memory solution or a license from its family of existing off-the-shelf products.
In conclusion, when it comes to reducing your next chips power consumption and the off-the-shelf offerings just do not cut it, contact sureCore and we will work with you to create an optimised solution that will help you meet your power budget.
Just remember; don’t forget the memory!
