Xilinx, Inc. and its Certified Xilinx Alliance Program Member Barco Silex are collaborating on video over IP solutions to deliver a platform combining hardware-validated IP, reference designs and systems integration services to support the company’s All Programmable FPGAs and SoCs. This has the potential to deliver quicker product development for broadcast equipment OEMs and enables the latest video over IP capabilities to be added to existing and new products.

“The broadcaster’s migration to IP-based infrastructures is complicated as industry standards are in a state-of-flux, which in turn puts pressure on equipment manufacturers to implement these emerging standards. Manufacturers can now benefit from a ‘one-stop-shop’ for a comprehensive FPGA-based platform to develop ‘future proof’ IP video solutions,” said Ben Runyan, Director of broadcast and consumer segment marketing at Xilinx.

“Not only can these manufacturers leverage the reprogrammable nature of Xilinx’s 7 series FPGAs to ensure their products can comply with changes to standards, our programmable platform can speed product development and enable OEMs to focus on innovative features and functionality.”

Barco Silex will serve as the system integrator and will focus on integrating a wide range of IP cores from Xilinx (SMPTE 2022, SMPTE SDI, Ethernet MACs) and Barco Silex (JPEG2000, high-performance memory controller) and will aim to solve the inherent system integration difficulties in shared memory systems with multiple IP blocks, and ultimately stitching multiple video streams together into a working system. 

The joint platform supports faster product design through the integration of video interfaces, processing and compression cores as well as the integration of different video over IP protocol standards (such as SMPTE 2022). 

Additionally, the platform enables the integration of multiple channels of video over IP, which can really increase the number of channels supported in each rack unit.  This increased channel density can reduce overall system cost through real estate savings, as well as potential power savings through having fewer devices and cards supporting the same number of channels in more dense architectures.