Cadence Design Systems has announced that TSMC has adopted Cadence solutions for 16nm FinFET library characterisation. Developed in collaboration between Cadence and TSMC, the library characterisation tool setting is available to TSMC customers for download on TSMC-Online. The setting is based on Cadence Virtuoso LiberateCharacterisation Solution and Spectre Circuit Simulator, and includes environment setup and sample templates for TSMC standard cells.
Utilising native Spectre API integration, the combination of the Liberate solution and Spectre Circuit Simulator delivers superior convergence and accuracy, enabling mutual customers to speed up their library characterisation cycle. In testing performed with TSMC, the combined Cadence characterisation and simulation solution reduced the turnaround time by half for 16nm FinFET standard and complex cell-characterisation cycles. As a result, TSMC has incorporated the Liberate solution with Spectre Circuit Simulator into its library characterisation production flow for the latest 16nm FinFET libraries. Libraries characterised by the Cadence characterisation solution were used in the 16nm FinFET v1.0 static timing analysis (STA) tool certification, including the CadenceTempus Timing Signoff Solution and other STA tools. The reference kit gives TSMC customers the tools needed to enable re-characterisation that addresses their specific design challenges with a consistent methodology that meets TSMC’s stringent accuracy and performance requirements. The Liberate solution also continues to support third-party circuit simulators.
“Library characterisation is an important part of 16nm FinFET collaboration with TSMC,” said Tom Beckley, senior vice president, Custom IC & PCB Group at Cadence. “Through this collaboration, customers can benefit from improved throughput, accuracy and capacity required for 16nm FinFET library characterisation.”
