Edward Ong, Product Marketing Manager at Power Integrations explores   achieving zero-watt standby by optomising each section of the power supply

Low load or standby conditions apply when the power supply is still active and must provide a ­regulated output to deliver power. No-load typically relates to power adapters or chargers when the load is disconnected, but the adapter is left plugged into the AC mains. These two conditions present different challenges.

Figure 1 shows a flyback power supply design for a notebook adapter optimised to achieve low standby and no-load consumption. 

Optimised SMPS’ using Power Integrations’ (PI) TOPSwitchÍ-JX are 65W power supplies (DER-243) (DER-243) capable of providing a 3.42A, 19V output at more than 86 percent efficiency, yet also achieves a no-load consumption of less than 90mW at 230VAC.

The design utilises a TOPSwitch-JX controller and driver IC (U1) from the company. The goal of the design was to produce a very compact notebook adapter that operates at high efficiency, has a low parts count, provides excellent load response, has latching overvoltage protection, and de-rates the MOSFET switch to 80 percent for ­ultimate reliability.

The devices maintain almost constant efficiency across a wide load range without using special operating modes to meet specific load thresholds. This improves performance to meet existing and emerging energy-efficiency regulations. However, when the goal is to achieve a sub-100mW no-load consumption for the entire circuit, every opportunity to save power must be exploited.

Major contributions to reducing no-load power consumption can be made at the line sensing network and the input filter, although there are many other opportunities for significant savings.

The V input of U1 provides the functions of overvoltage (OV), undervoltage (UV), line feed forward with DCMAX reduction, output overvoltage protection (OVP), and remote ON/OFF. The line sense resistors R3 and R4 provide a line condition input to U1 and also provide the required minimum bias current of 25µA.

The standard value for these resistors is 4MO. However, at 230VAC input, this would result in a power drain through these resistors of 30mW. In DER-243, the line sensing resistance (R3 + R4) was increased from 4MO to 10.2MO to reduce this no-load input power dissipation by ~16mW. This required the addition of R20 to provide additional bias current and maintain the same line undervoltage threshold.

Resistors R7, R8, and R9 reduce the external current limit of U1 as the line voltage increases. This allows the supply to limit the output power to <100VA at high line, while still delivering the rated output power at low line, and to provide a nearly constant output over-load power level with changing line voltages.

The clamp network (VR2, C4, R5, R6, R11, R28, R29, and D2) limits the peak drain voltage spike caused by leakage inductance to below the BVDSS rating of the internal TOPSwitch-JX MOSFET. Under light or no-load conditions, the leakage inductance energy and switching ­frequency are lower.

In a standard RCD clamp, the capacitor C4 would then be discharged and recharged each cycle, wasting a significant amount of energy.

The RZCD arrangement solves this problem by preventing the voltage across the capacitor discharging below a minimum value (defined by the ­voltage rating of VR2) and therefore minimising clamp dissipation under light and no-load conditions. At the AC input, filtering is provided by common-mode inductors L3 and L4. X-class capacitor C1 provides differential filtering, and resistors R1 and R2 provide a path for C1 to ­discharge.

This safety requirement prevents any potential electric shock. Safety standards (UL1950 and EN60950-1) mandate that the voltage must be discharged with a time ­constant of less than 1 second for capacitance values above 100nF.

The presence of these resistors is undesirable from a power budget standpoint because they represent a continuous dissipation of 12mW at 230VAC.

New PI CAPZero ICs contain an integrated loss-of-AC detector and back-to-back MOSFETs in an SO-8 package. When the AC input voltage is present, the device remains in an OFF state, blocking current flow in the ­discharge path and eliminating power losses.

When the AC is removed, the IC device turns on, thereby switching in the resistors and allowing discharge of the input filter capacitance. The ICs are self-powered from the AC line, with a ­current ­consumption of less than 21µA.

Sense resistors still draw significant energy from the AC mains, regardless of whether the switching IC U1 is operational or static. This power drain can be eliminated with the use of a SENZeroÍ device, which comprises two or three 650V MOSFETs with internal gate drive and protection circuitry.

When the system enters standby, the VCC falls and gate drive is removed from the MOSFETs. The MOSFETs then switch to high impedance and isolate the current paths from the high-voltage DC rail. The power losses are consequently reduced to significantly below 500µW per channel.

By using advanced ICs, remarkable results can be achieved.

Power Integrations