Synopsys, Inc. has released its DesignWare AEON Trim NVM IP for high-voltage processes. The new IP is claimed to be up to 75 percent smaller than alternative NVM IP solutions, which can help reduce the size and cost of automotive ICs. This technology is available in standard 180 nanometer 5V CMOS and Bipolar CMOS DMOS (BCD) processes without a need for additional masks or process steps. The DesignWare NVM IP supports the wide temperature range required for automotive Grade 0 applications and exceeds AEC-Q100 quality standards. In addition, faster programming times reduce NVM test times by up to three times, in comparison to alternative NVM solutions. This can potentially enabling reduce production test times and minimise test costs for automotive and industrial ICs.
ZMDI’s robust AEC-Q100-certified ICs provide advanced sensor-signal conditioning and configurability, and integrating the DesignWare AEON Trim NVM IP will help to ensure high data retention and reliability while minimising area and test times,” said Dr. Michael J. Ohletz, executive vice president, global and strategic quality at ZMDI. “Designers selecting components for demanding and harsh under-the-hood automotive environments look for proven IP solutions that can reliably perform crucial safety functions for 15 or more years. ZMDI selected Synopsys NVM IP because the IP met our rigid specifications and because of our shared commitment to producing reliable, high quality products.”
With the growth in the automotive IC market, designers need to meet the quality and reliability criteria established for the extreme environment under the hood of a car while respecting the cost and size parameters of even the smallest ICs. With its Grade 0 temperature range and 15+ year data retention capabilities, the DesignWare AEON Trim NVM IP for high voltage processes enables designers to implement their ICs in applications with harsher and safety-critical environments.
This release includes special test modes that increase programming speed and reduce test costs and time by up to three times. For example, the IP includes bulk operations that enable designers to program the entire array in a single, faster operation. In addition, designers can select test conditions and test limits that emulate temperature effects, thereby eliminating the need for testing across temperature.