Communications infrastructure, imaging equipment, industrial instrumentation, defence electronics and other multi-channel, data-hungry systems are demanding wider resolutions and higher sampling rates from the data conversion stage.
Physical layout constraints of the parallel interface and bit-rate limitations of the serial LVDS (low-voltage differential signalling) approach are beginning to present technical barriers for designers.
To address this need, Analog Devices, Inc. has introduced its AD9250 dual-channel, 14-bit, 250-MSP A/D converter featuring the JEDEC JESD204B serial output data interface standard.
The converter comes with full JESD204B Subclass 1 deterministic latency at 250 MSPS. This functionality accommodates the precise synchronisation of multiple data-conversion channels through a serial interface.
The converter’s serial interface implementation provides up to 5Gbps over a 1 or 2 lane-capable link. Two serial lanes are used to support the full 250-MSPS, dual A/D converter data rate, or a single lane can be used to support reduced sampling rates.
This converter’s JESD204B serial interface reduces the number of high-speed differential output data paths required from as many as 28 to just two per IC. Its Subclass 1 deterministic latency function is repeatable from power-up cycle to power-up cycle and across link re-synchronisation events.
Areas where this function is important are in diversity radio systems and instrumentation, multi-mode digital receiver applications such as TD-SCDMA, WCDMA, LTE (especially the 2R2T >8R8T evolution), radar/defence electronics, medical imaging systems, cable infrastructure and general-purpose software radios.
Analog Devices
http://www.analog.com/AD9250
