A collaborative effort between Entegris, Inc. and Imec Institute will focus on advancing the development and broadening the adoption of 3D integrated circuits.
3D IC technology is a process by which multiple semiconductor dies are stacked into a single device this is claimed to have the capability of increasing functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics such as smartphones and tablets that require smaller ICs which consume less power.
One of the key steps in 3D IC manufacturing process entails thinning semiconductor wafers while they are bonded to carrier substrates.
Handling such thinned 3D IC wafers during the production process can result in wafer breakage, edge damage, and particle generation. A standardised, fully automated solution that supports the handling of multiple types of wafers would result in a significant cost reduction and pave the way toward further development and scaling of 3D IC technologies.
The two companies are working on creating a solution to safely transfer and handle multiple kinds of 3D IC wafers without the risk of breakage and other damage that may occur during the 3D production process.
Our current collaboration is aimed at leveraging our wafer handling expertise and technology to reduce contamination and breakage by applying full automation to the handling of thin wafers during 3D wafer production. said Bertrand Loy, president and CEO of Entegris.
This project builds on our previously completed work with Imec to develop dispense and filtration methods to reduce bubble and defect formation during the dispense of material that is used to temporarily bond 3D wafers to carrier substrates,” said Loy.
”This collaboration with Entegris aims at developing a solution toward fully automated handling of multiple types of 3D IC wafers,” stated Eric Beyne, Director of imec’s 3D integration research program. “Such a general solution would imply a significant reduction of the development cost, which is key to the realisation of a scalable and manufacturable 3D IC technology.”