Gordon Hands, Director of Consumer/Mobile Product Marketing at Lattice Semiconductor explores how FPGAs are advancing in consumer devices
Over the last twenty years, there have been dramatic improvements in the power consumption of FPGA devices. To illustrate (Figure 1), in 1995 devices with a capacity equivalent to today’s smallest FPGAs had a static power (the power not associated with clocking) in the range of 0.5W.
By 2002 this had been reduced to below 5mW, and by 2010 to below 50uW. Although not quite as dramatic, dynamic power (power associated with device switching), driven by a reduction in operating voltage and interconnect capacitance, has been reduced by over ten times over the same period.
The parallel logic-based nature of FPGAs also presents some interesting system-level opportunities for power reduction. These opportunities fall into two broad categories. The first is a group of applications for the management of information polling and determining whether action is required.
The parallel logic-based FPGA can often implement this using less power than the most common alternative, which is to continually run a microprocessor to determine if an event that needs action has occurred.
The second category is a group of applications for offloading tasks that can be implemented more efficiently in a parallel fashion within an FPGA. This enables the main microprocessor to operate at a slower frequency.
The combination of low power consumption with the ability to allow designers to architect for lower power, is leading to a host of innovative new FPGA applications. These applications are finding use across a wide range of equipment types.
This adoption of innovative new approaches has been driven by design challenges that include the need to increase battery life and to reduce power in order to meet new environmental regulations. Here are some examples:
Sensor hub for mobile electronics
There has been a proliferation of sensors within common mobile consumer devices such as smart phones and tablets. Typical sensor examples include ambient light, touchscreen, proximity and accelerometers.
In order to provide users with the experience they expect, these sensors need constant monitoring. However, this monitoring limits the amount of time that the application processor can spend in its sleep mode.
The low static power of some of the latest FPGAs, such as Lattice’s Custom Mobile Device, enables them to be used as a preprocessor for sensors in these mobile applications (Figure 2).
The FPGA can manage the polling of the various sensors, most normally done through I2C, and determine, based on activity, whether to wake the application processor in order to act on this information.
Wake-on-LAN for wall plug consumer electronics
Many consumer electronic devices such as TVs, set-top-boxes and printers are connected to Ethernet-based networks. It is often desirable for these devices to be brought out of their standby mode via the network.
This is typically achieved by sending a so-called ‘magic packet’ that must be received by the device and used to imitate the exit from standby. However, leaving the microprocessor subsystem powered in order to monitor for the magic packet can be problematic in terms of additional power consumption.
This is especially true given the latest environmental regulations that often limit standby power to 0.5W or lower. An alternative approach is to use an FPGA to monitor the incoming packets from the physical layer device and wake the microprocessor when the magic packet is detected.
Frame buffer
Many equipment types use LCD or similar displays. With these displays, it is commonly necessary to keep sending data at the expected frequency, often 60 times a second. If data is not sent, the screen will go blank. This is inefficient, as there are many occasions where an image is required but the microprocessor subsystem can be in standby.
In industrial applications this is often the case where a touch screen is waiting for operator input. This case is also common in consumer electronics, when the user is reading a static screen (such as in an e-reader application).
With their flexible IO structures, FPGAs can be used to build frame buffers that accommodate different display standards such as RGB and LVDS, along with a wide selection of memory devices such as LPDDR, DDR1 and DDR2 that are required to buffer data.
The logic within the FPGA can be used to implement custom algorithms to support the switching between normal and buffered modes as required.
Image manipulation for mobile applications
Today’s mobile devices are making increasing use of image data. This can be in the form of inputs, such as cameras, or outputs, such as displays.
There are many processor-intensive functions that are commonly used along with this image data. On the output side, display scaling is often needed to support a secondary output such as a TV or monitor.
Another common function is the rotation of output data in response to the user changing the orientation of the device. The parallel structures in the FPGA allow for efficient implementation of these functions, enabling power saving when compared to a microprocessor implementation. On the input side, an increasing interest in gesture recognition is creating interest in efficient image analysis.
This class of functions is already commonly implemented in FPGAs for security and surveillance applications, and is now an area of potential use in mobile applications.
Lattice Semiconductor
www.latticesemi.com Enter 207Over the last twenty years, there have been dramatic improvements in the power consumption of FPGA devices. To illustrate (Figure 1), in 1995 devices with a capacity equivalent to today’s smallest FPGAs had a static power (the power not associated with clocking) in the range of 0.5W.
By 2002 this had been reduced to below 5mW, and by 2010 to below 50uW. Although not quite as dramatic, dynamic power (power associated with device switching), driven by a reduction in operating voltage and interconnect capacitance, has been reduced by over ten times over the same period.
The parallel logic-based nature of FPGAs also presents some interesting system-level opportunities for power reduction. These opportunities fall into two broad categories. The first is a group of applications for the management of information polling and determining whether action is required.
The parallel logic-based FPGA can often implement this using less power than the most common alternative, which is to continually run a microprocessor to determine if an event that needs action has occurred.
The second category is a group of applications for offloading tasks that can be implemented more efficiently in a parallel fashion within an FPGA. This enables the main microprocessor to operate at a slower frequency.
The combination of low power consumption with the ability to allow designers to architect for lower power, is leading to a host of innovative new FPGA applications. These applications are finding use across a wide range of equipment types.
This adoption of innovative new approaches has been driven by design challenges that include the need to increase battery life and to reduce power in order to meet new environmental regulations. Here are some examples:
Lattice Semiconductor
