A new FPGA family has been recently annonunced by Lattice Semiconductor. The devices features DSP blocks and hard IP-based communication engines for cost- and power-sensitive wireless, wireline, video, and computing markets.
The LatticeECP4 devices are ideal for developing mainstream platforms for a variety of applications such as remote wireless radio heads, distributed antenna systems, cellular basestations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission and data centre computing.
The FPGAs contain up to sixteen CEI-compliant 6Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both low-cost wire-bonded and high-performance flip chip package types.
This gives the choice to deploy the FPGAs in chip-to-chip as well as long haul backplane applications.
The configurable SERDES/PCS can be integrated with the hardened communication engines to economically build high bandwidth sub-systems.
The devices offer up to ten times the power and cost reduction of similar implementations in FPGA fabrics.
