Philipp Hudelmaier at Fujitsu Semiconductor Europe explores the latest in prototype chip development for in-vehicle driver assistance systems
In the field of driver assistance, new functionality has special requirements that are poorly served by the standard chip solutions available, due largely to performance, feature set and price. Companies such as Fujitsu are tackling this problem head-on by offering a cost-optimised process for custom chip development work.
One example of features offered by this process is the option of integrating algorithms tested on the development PC or FPGA into a chip, which ultimately enables evaluation on the target hardware with real-world computing power. Starting with the application’s requirements, development work is conducted in close collaboration with the customer, who can access design services and an extensive IP portfolio offered by the company and its business partners.
As well as offering short prototype runs, the process also gives developers the option of simple migration to high volume production.
The increasing levels of functionality and complexity for in-vehicle driver assistance features are accompanied by a new set of challenges for both the chip technology and the development process. Features such as adaptive cruise control or emergency brake assist provide us with typical examples.
These features process sensor data and camera images, consolidate data and use highly complex algorithms to assess current driving conditions. To meet real-time requirements, such systems make particular demands on the hardware, which provides specialised interfaces to enable the polling of the sensor and image data and supports processing of the consolidated data by applying an extensive suite of algorithms.
The interfaces and the computing power supplied by standard chip solutions result in a configuration that is less than ideal. Accordingly, research units use mainframes or research computers to perform initial evaluation of algorithms. Advance development specialists then use these results to implement the algorithmic logic on programmable chip solutions. During the process of development into a series product, a solution transition is made from a programmable chip to a custom chip. This solution offers lower-cost properties in terms of unit price and efficiency.
This transfer starts only once algorithms are already very mature, due to the high costs of development work. Yet this procedure presents a particular problem: the application can be evaluated on the real-world target hardware only shortly before series maturity. In addition, any changes required in the design can lead to scheduling delays.
The development process
Research and development work for complex driver assistance applications often starts by utilising mainframes or PCs, which are able to provide the computing power needed for such demanding tasks as image processing algorithms, see (Fig. 1).
Integration into a simulated environment – which supports the loading of real vehicle and sensor data – is the next step, enabling an initial evaluation of the algorithms. This is followed by the advance development phase, which describes the algorithmic logic at the register transfer level (RTL).
Based on the system architecture and computing power requirements, the functions are then designed using FPGA technology, culminating in an evaluation phase at the component level. As series development starts, the components are integrated into a system and evaluated.
As soon as initial results permit, the design for a custom chip solution is then started in parallel, based on the RTL descriptions of the algorithms. The first step in this process is to reprogram the RTL from an FPGA-oriented structure into a format that fully exploits the possibilities of a standard cell implementation. Once the custom chip is available, this then supplants the FPGA solution and the test phase with series hardware starts.
To manufacture custom chip solutions, a procedure is required that enables the early transition of research and developments results (e.g. algorithms for object recognition, etc.) – and at a justifiable price point – to a semiconductor solution that is near-production quality.
The procedure desired needs to offer a development path from advance development through the system prototype phase to series production that avoids making significant structural changes to the prototype modules (such as avoiding the transition from programmable logic to custom design).
Ideally, this procedure should achieve time savings in the development phase while also minimising risk.
From the initial concept to the final semiconductor device for volume production, numerous development milestones need to be passed. Fujitsu has developed an approach that offers a well-defined, well-supported development flow for applications that in many cases lead to a customer-specific chip.
With focus on automotive applications, where special design rules regarding automotive standards such as AECQ-100 and functional safety according to ISO 26262 exist, the process of the company envisages a collaboration with the customer at a very early stage as illustrated in Fig. 2.
Depending on experience, the specification is produced by customers themselves, in the form of an RTL description in VHDL or Verilog.
Alternatively, one can also work with an external design unit such as the Fraunhofer Institute for Integrated Circuits (Fraunhofer IIS), with whom Fujitsu has enjoyed a long and successful working relationship.
With this option, the customer receives a comprehensive support package that starts with the specification phase, includes synthesis, layout and verification, and covers the creation of manufacturing data for prototyping.
IP portfolio for development
For development work to be effective, the team needs to be able to access pre-developed intellectual property (IP) for standard functionality such as CPU cores, memory controllers and interfaces (CAN, USART, …) see (Fig. 3).
Fujitsu meets this need with an IP portfolio from the company and its partners, characterised in particular by hard IP with predefined layouts optimised for specific technologies, and a strong focus on analogue functionality such as PLLs, ADC or DAC and I/O components for standard interfaces such as USB 3.0, PCI and DDR2/3. The majority of IP items are provided as technology-independent RTL code.
Supplementing Fujitsu’s IP, developers can also draw on IP that the company has licensed from external suppliers. This IP includes the Cortex CPU cores from ARM, for example, plus the corresponding peripherals, or the Automotive Pixel Link (APIX) interface from Inova Semiconductors.
Following the full description of the component in an RTL format such as Verilog or VHDL, a simulation is then used to test the interplay of the IP deployed with the specific logic blocks in terms of functionality and speed. In the next stage, Fujitsu or a qualified design firm applies circuit synthesis to transpose the RTL description into the technology libraries provided by the company, followed by layout and manufacturing data (GDS) creation work. Verification then follows, in which static timing analyses, RTL vs. GDS comparisons and extensive design rule tests are utilised to verify if the GDS data set is error-free and to prepare for prototype manufacturing.
With this approach, prototype manufacture is completed with the help of the Multi-Project-Wafer (MPW) developed by eShuttle, a Fujitsu and Advantest subsidiary, using direct-write electron-beam lithography.
Within this programme, prototypes can be manufactured in 90nm, 65nm and forthcoming 55nm technologies (see Fig. 4). The procedure involves the manufacture of multiple separate projects on a single wafer at predetermined production start dates.
The wafer is subdivided into predefined blocks of e.g. 5 by 5mm for 90nm technology: customers can then reserve these for projects and receive 30 samples after processing. More samples can be requested as required. Larger chip areas can be achieved by consolidating multiple blocks.
With the latest technologies, the costs of manufacturing for the 40-50 exposure masks required – depending on process options – make up a considerable portion of development costs.
By utilising eShuttle’s direct-write electron-beam lithography, masks are required only for the process steps used to produce the basic wafer.
The further steps for the 7-10 metal layer for the wiring are written directly to the wafer by the electron beam, without using masks. This approach saves a significant proportion of the costs of manufacturing for masks. Since exposure times are correspondingly longer, it is advisable to limit the number of samples manufactured.
With this approach, manufacturing costs for prototypes can be reduced by approximately 80-85 percent of the costs for a complete set of photo masks, which significantly lowers the cost barrier to entry for chip development.
The prototype development path as described here is based on the same technologies, libraries and development methodologies that are deployed for high-volume production runs. This ensures reliable and highly risk-minimised migration to the series production stage.
Ideally, no layout changes would even be required, just the creation of the complete photomask and manufacturing infrastructure setup, such as assembly, test programme generation and product qualification.
At a moderate price point for the MPW sample production, customers receive a near-production quality prototype environment that is usable well into later testing phases. Product generation, which then incurs costs for the full set of photo masks and qualification, is triggered only shortly before series components are required.
As Figure 1 shows, in taking this approach to series chip development, companies such as Fujitsu achieve time savings in the workflow that imply a substantial risk safety margin since the target system evaluation can be executed at an earlier stage.
In principle, this approach to development is not limited to specific fields of application such as driver assistance. In this context, driver assistance should merely be seen as a useful example, since it has the following key features: Suitable standard chips are not available, the field of application requires differentiation with customer-specific hardware solutions, near-series quality chips are required for safe and realistic system testing and series deployment in medium to high unit volumes is envisaged.
Philipp Hudelmaier is System Engineer at Fujitsu Semiconductor Europe