Frank Schirrmeister at Cadence Design Systems considers the benefits of early optomisation for low power designs and how to best utilise this
Low power has become increasingly important for electronic design and drives a lot of decisions for pure semiconductor hardware design as well as for software optimisation and early hardware/software co-design.
Early power optimisation is facing the classic system-level dilemma: the earlier a decision can be made, the higher the potential effect of the decision will be, but because the decision is made early, it has to be made based on limited information. Design flows are changing to allow more frequent confirmation of decisions based on refined data, allowing decisions to be made earlier and checked more often.
Low power optimisation today focuses on lower levels of implementation. While the gains have been considerable, attacking the problem at the system level can lead to even greater gains. An earlier approach, however, creates new challenges for modeling and analysis.
While considerable optimisation can be achieved by turning off the clocks that are fed into gates, developers are now looking at completely powering down larger areas of their design or are using variable voltages to tradeoff between performance and power. The software drivers controlling these effects have to be written, verified, and debugged, making this a hardware/software integration challenge.
Power analysis using virtual prototypes with transaction-level models (TLMs) allows power management policies to be tested, and enables relative software power optimisations. Power figures will not be accurate enough to predict the exact power, but will allow users to find out if a change would result in relative savings.
This is particularly true of a loosely timed (LT) TLM virtual prototype-at this level of timing detail, tools can only provide figures for the estimated power consumed per function. When the timing is refined down to the approximately timed (AT) level, tradeoffs are then possible between performance and power since the virtual prototype will now be able to provide profiles of power over time.
As indicated in Figure 1, hardware components can be characterised by a set of power parameters that are then used to calculate the power of the individual block. These are then accumulated by a central logging module for analysis. Virtual platform also allows early development of the required power management drivers that will help decide when certain portions of the design can be switched to a different power state.
The underlying challenges
While the aspects of annotating the parameters (as indicated in Figure 1) is in itself not difficult, the actual challenge lies in measuring the right data to be annotated. Users today will simply run analysis based on power estimates, measurements from previous designs, or measurements based on refined data as it becomes available while the design flow progresses.
Power analysis using RTL or gate-level descriptions
Once a design has been refined to the register-transfer level (RTL), two big challenges have to be addressed: Efficiently, articulating the actual low-power intent to drive analysis, and effectively collecting the right amount of toggle information during execution to understand low-power effects.
System-on-chip (SoC) power analysis requires long runs to identify and analyse peak and average power at the system level to avoid limiting the analysis to potential local maximum power consumption cases. RTL simulation alone is not capable of doing that- it needs to be efficiently augmented by hardware-assisted techniques such as those offered in an Verification Computing Platform from Cadence, called Palladium XP. Using hardware-assisted verification, users have a real test environment that factors in the software impact.
This platform contains a high-speed low-power calculation engine for tradeoff analysis between speed and accuracy. Toggle information about design activity can be collected. A fast, coarse-grain analysis using native toggle counts is fastest to create and provides raw design information. If peak identification with higher accuracy is the objective, then weighted toggle count provides weights on different nets. For highest accuracy, a fine-grain analysis can use the full toggle count format.
For power-aware functional verification, the low-power intent can be modeled in the Common Power Format (CPF). This platform then reads the CPF file and automatically creates the instrumentation logic for low-power operations. Low-power activities can be captured and shown in waveforms for debugging. Palladium DPA is aware of the power intent captured using CPF, which allows the DPA report to be complete with power mode and power domain information.
The techniques outlined here at the TLM and RTL levels are all working well for their specific target use models. Going back to earlier in this article- following the paradigm of deciding early and verifying often with refined data-next-generation power optimisation flows will combine the techniques at the different levels of abstraction, as indicated in Figure 2.
Starting from TLM-based virtual platforms, power intent can be declared and forwarded to implementation in RTL. Once refined, more detailed measurements become available, data can be back-annotated into the earlier phases of the design. That linkage can go all the way back into the static data analysis as it is provided for IP blocks.
With a connected flow from TLM through RTL to implementation, users will be able to further optimise designs for power and performance, meeting the ever-growing demands that consumers have for the latest electronic gadgets.
Cadence Design Systems
