Enhancements have been added by Xilinx to the company’s Vivado Design Suite, with the release of its Design Suite 2013. This includes a new IP-centric design environment for accelerating the time to system integration, and a comprehensive set of libraries to accelerate C/C++ system-level design and high-level synthesis (HLS).
The company advises, to accelerate the creation of highly integrated, complex designs in All Programmable FPGA devices, it has delivered the early access release of its Vivado IP Integrator (IPI).
This platform is able to speed the integration of RTL, x IP from both the company and third party IP and C/C++ synthesised IP.
Based on industry standards such as the ARM AXI interconnect and IP-XACT metadata for IP packaging, this platform is said to deliver intelligent correct-by-construction assembly of designs cooptimised with All Programmable solutions from the company.
This IP Integrator is a device and platform aware interactive, graphical and scriptable environment that supports IP-aware automated AXI interconnect, one-click IP subsystem generation, real-time DRC, interface change propagation, and a powerful debug capability.
When targeting a Zynq-7000 All Programmable SoC, embedded design teams can now more rapidly identify, reuse, and integrate both software and hardware IP targeted for the dual-core ARM processing system and high performance FPGA fabric.
Xilinx
