Brian Caslis, Lattice Semiconductor Corporation discusses how FPGA design challenges are being met with a new software environment for design exploration, to achieve key cost and performance capabilities
FPGAs are being used increasingly in more cost sensitive, power sensitive, high volume applications. To meet the challenges these applications present, designers need an easy to use, flexible design environment for exploring different design implementations to achieve their cost, power and performance targets. In response to these needs a new design software environment has been created by Lattice Semiconductor.
The company’s Diamond software environment integrates an advanced platform of engines, I/O placement technology, IP reuse technology, accurate power calculation and SSO analysis, and hardware/software system design. However, it expands available functionality from previous design tools in three key areas: design exploration, ease of use, and improved design flow.
A key feature for design exploration is the addition of expanded project capabilities, including the concepts of ‘implementations’ and ‘strategies.’ Key improvements to design projects include the following features:
• Implementations allow multiple versions of a design within a single project for easy design exploration. The primary purpose of these implementations is to define the structure of the design
• Strategies allow implementation ‘recipes’ to be applied to any implementation within a project, or shared between projects. Strategies tell the software tools how a design should be run or implemented
• Projects allow the mixing of Verilog, VHDL, EDIF and schematic sources within any implementation
• Multiple files are supported for constraints, timing analysis, power calculation, programming and hardware debug tools
• Run Manager view allows the processing of multiple implementations in order to explore design alternatives for the best results. It allows results to be compared across multiple implementations
Implementations define the design structural elements for a project, including source code, constraint files, and any debug insertion. An implementation can be thought of as the raw material necessary to create the design. A common usage for multiple implementations within a project would be to evaluate different architectures to determine which produced the best results. For example, one implementation of a design may use inferred memory, while another implementation may use instantiated memory.
The project structure provides several key benefits. A single project type can handle a variety of input source types and allow the management of multiple constraint, debug and analysis files. Additionally, through the use of implementations and strategies, a single project can accomplish what would have taken several projects using other design tools perhaps.
User interface allows ease of use
The user interface combines new features while offering further ease of use. All the tools now open in ‘Views’ are integrated into a common user interface; tools can also be detached in separate windows. New features like the Start Page and Reports View allow easy access to information. The user interface includes several key features:
• Common menu and button locations
• Three main sections of the user interface for tools, projects, and output
• Tool view window pane provides the ability to detach, attach, arrange and split for side by side viewing of the tools
• Project view window pane provides the ability to detach, attach, and arrange views such as File list and Process views
• Output view window pane provides the ability to detach, attach, and arrange views such as outputs, errors, warnings, and TCL console
• Start Page provides direct links to opening projects, importing the company’s ispLEVER design tool projects, online help, and all software updates
• Report view provides a centralised location for all reports from implementation tools
Advanced feature set
The user interface also offers new views to ease specific tasks. In addition to the new Start Page and Reports view, the new ECO Editor and Programmer allow the direct editing of the physical netlist for a few common functions and an improved way to reprogram an FPGA once the initial setup has been completed.
Several improvements have been made specifically to offer a better design flow.
The new Timing Analysis view (figure 2) offers an easy to use graphical environment for navigating the timing information details.
A key benefit in the new Timing Analysis view is that timing constraints can be changed and the analysis re-run without having to update the implementation. This results in significant time saving for very large designs.
The Simulation Wizard guides users through all the steps necessary to export a design to a simulator in the format desired, such as simulating the RTL design or the gate-level timing design.
For scripting support, the software adds specific Tcl command dictionaries that are available for projects, netlists, HDL code checking, power calculation, programming, and hardware debug insertion and analysis.
Scripts can be run in the console view, a separate application, or from command line shells.
The software features advances in design exploration, ease of use and improved design flow over previous generations of software. These capabilities are well suited to assist designers targeting low power, cost sensitive applications using FPGAs.
Lattice Semiconductor Corporation