Reza Asgari, Wafer Scanner Product Manager at Rudolph Technologies Inc., explores how a new wafer scanner system enables 2D/3D bump metrology and inspection for advanced packaging processes

Critical three dimensional (3D) inspection and measurement capabilities are required for rapidly emerging advanced packaging applications. Many of these new processes use small metallic contacts, generically known as bumps, to provide connections to the internal elements of the integrated circuit.

Although originally developed to provide a greater number of contacts per die as the complexity of individual integrated circuits (IC) increased, bumps have now become an integral part of many 3D integration (3DIC) schemes; that seek to increase the speed and functionality of electronic devices by connecting multiple stacked die with complex technologies such as through silicon vias (TSV) and redirect layers (RDL).

As do all processes used in IC fabrication, these new technologies require careful control to minimise the process variations and inspection to detect defects.

From its earliest days, the design and fabrication of integrated circuits has been primarily a layer-by-layer exercise in two dimensions (2D). The most complex ICs manufactured today are built on a single layer of transistors, though these are overlaid by ­multiple layers of interconnecting pathways.

Even the well-known Moore’s Law concerned itself with decreasing sizes and increasing density in 2D. As the underlying physical principles of electronic devices have made 2D size reductions increasingly more difficult to achieve, designers have turned their attention to the third dimension to continue to meet the market’s seemingly insatiable demand for ever increasing speed and power in ever decreasing space.

This shift in emphasis to the third dimension is occurring at all scales, including the design of individual transistors, but is most evident in technologies that stack multiple chips in a single package to create 3DICs.

Bumping processes were originally developed to address the need for more I/O paths. In conventional processes, I/O pads were arranged around the edges of the die and connected to the package leads by very fine wires.

When the availability of space at the edges becames a limiting factor, engineers developed processes that permitted the contact pads to be located over the full surface of the die, greatly increasing the number of I/O connections possible.

A critical element in these processes was the fabrication of solder bumps on the pads, which provided the necessary physical and electrical contact when fused to a matching array of package contacts. The size, location, and particularly the height of these bumps required careful control to ensure reliable connections.

Many of the advanced packaging processes now coming into production incorporate some form of bumping process to provide connections among the stacked chips. A typical process also includes redirect layers to route signals from the circuit to the bump and through silicon vias to provide vertical pathways through the silicon substrate of each chip.

These TSV may also be terminated by a bump as part of the connection scheme. Although similar in concept to foregoing bumping processes, the bumps used in these 3DIC interconnects are often much smaller and more closely spaced.

A bumping process provides multiple opportunities for inspection and metrology at incoming inspection.

Defects can generally be grouped in the following three categories:

• Defects on the surface of the wafer such as foreign material, etch residue, holes in the passivation layer, etc. These are typically macro defects larger than 3um but may be as small as 1um.

• Defects related to bumps such as missing bumps, bridges between bumps, nodules, etc.

• Defects in the critical dimensions of the bumps, such as bump height, coplanarity, bump diameter, bump true position.

• The inspection of bump height and coplanarity are referred to as 3D measurements and all others are 2D.

The WS3880 from Rudolph Technologies is a new Wafer Scanner that provides both 2D bump/surface defect inspection and 2D and 3D bump dimensional inspection in one system.

It incorporates a new ultra-high resolution 3D sensor, designed specifically for micro bumps having diameters and pitches as small as a few microns. It also includes a 300mm chuck mounted on an air bearing stage and a 2D TDI line scan camera.

The system makes separate passes for 3D and 2D inspections, one pass with the TDI camera and a second pass with the laser. The TDI camera can use bright field or dark field illumination, or a combination of both, to collect 2D images, which are compared against a golden reference to find defects.