Chandra Sekar Balakrishnan, Solutions Development Engineer at Xilinx Inc. explores designing with advanced FPGAs for low power and high performance in applications that demand these specifications.
As successive generations of high-density feature-rich FPGAs encourage ever greater system integration, engineers must consider power consumption from the earliest stages of the design cycle if they are to control issues such as the size and cost of the power-supply, battery life, thermal design and system reliability.
As feature sizes shrink with each generation of process technology, leakage current within the transistors tends to increase leading to higher static power consumption when the FPGA is not operating.
Dynamic power also tends to increase, as faster transistor switching performance allows the use of higher clock rates increasing power consumption in the programmable logic and I/Os. As FPGAs continue growing in capacity with each product generation, more logic means more leakage and more transistors operating at higher speeds per device. As a consequence, designers must act to meet system power and thermal-design requirements from an early stage of FPGA development.
Figure 1 describes the design cycle, from FPGA selection through low-power design techniques. Different types of action can be taken at various stages to reduce the overall FPGA power consumption.
During FPGA selection, it is important first to evaluate the process technology. FPGAs such as the Xilinx 7 series are based on a 28 HPL (28-nanometer High-Performance, Low-Power) process; a lower-leakage technology that eliminates the need for static-power management in the FPGA design. Comparable FPGAs built with the 28HP process may have no performance advantage but can consume more than twice the static power.
Migration from a larger prototype device to a smaller FPGA for production also effectively reduces power consumption, in addition to trimming cost. This can be relatively straightforward if using FPGAs based on a unified architecture.
Scaling the FPGA operating voltage also saves both static power and dynamic power. The headroom in the 28 HPL process (1.0V) and -2L (0.9V) FPGA varies to offer very low static and dynamic power without loss of speed-grade performance.
Operating at 0.9V reduces static power by around 30 percent. The voltage drop would also reduce performance, but 2L (0.9V) devices can be screened for speed and a tighter leakage specification.
This screening method can reduce power by 55 percent at worst-case process compared with the standard-speed-grade devices. Because dynamic power is proportional to VCCINT2, the 10 percent reduction in VCCINT reduces static power by 20 percent.
Low-power design techniques
There are numerous design tips and techniques to minimise power consumption. For instance, reducing the logic in the design wherever possible is vital, for example by using dedicated hardware blocks rather than implementing the same logic in CLBs. This reduces the total transistor count, allowing the use of smaller devices, lowering static and dynamic power.
As a general rule, inferred resources should be used as much as possible. These can be steered individually, or as a group, toward the FPGA fabric or silicon resource.
Assigning signals for control of synchronous elements such as clock, set, reset and clock enable can affect device density, utilisation and performance. Following a few guidelines will help minimise the power impact.
Using both a set and a reset on one register or latch should be avoided, since the underlying flip-flop can natively implement only one set, reset, preset or clear at a time. Additional controls consume extra FPGA logic.
Control signals should be active-high where possible. Active-low signals require inversion that consumes an LUT input and hence can increase runtimes and reduce device utilisation. If active-low polarity cannot be avoided, the inversion should be performed in the top-level hierarchy of the code.
Reducing unnecessary use of set and reset commands, which prevent logic structures such as shift register LUTs (SRLs), LUT RAMs and block RAMs from being inferred, can help improve placement, increase performance and reduce power. Many circuits can be made to self-reset, or simply do not need a reset.
Using BUFGMUX, BUFGCE and BUFHCE to gate an entire clock domain helps optimise clock and block activity. For applications that only pause the clock on small areas of the design, the clock-enable pin of the FPGA register can be used.
Other tips include placing intermittently used logic in a single clock region to prevent designs spreading across multiple clock regions. The tools will attempt this automatically.
Some designs may require manual effort. Limiting the movement of data around the FPGA, using fewer and shorter buses, and careful placing of pins and corresponding logic during floorplanning, are also recommended.
Effective use of partial configuration can save static as well as dynamic power. Designers can essentially time-slice the device and so use a much smaller FPGA, thereby saving static power. Swapping a high-performance configuration for a lower-power version of the same design, according to application requirements, can save dynamic power.
Similarly, I/Os can be reconfigured, for example to convert power-hungry LVDS I/Os to a lower-power interface such as LVCMOS at times when the application will allow. In some designs, I/O power is a major component of total power, especially in memory-intensive systems.
Low-power I/O standards such as HSLVDCI can save considerable power in FPGA-to-FPGA communications and lower-speed memory interfaces. Optimising slew rate and drive strength, and taking advantage of Digitally Controlled Impedance (DCI), also minimises power consumption in FPGA terminations.
Understanding and implementing power-sensitive design techniques in advance of coding is the most effective recommendation for reducing system power demands.
