Cadence Design Systems, Inc. has released the latest in its design software offering with the release of its Interconnect Workbench. This software provides cycle-accurate performance analysis of interconnects throughout the system-on-chip (SoC) design process, it identifies design issues under critical traffic conditions and enables users to improve device performance and can reduce time to market, it also works in conjunction with the company’s Interconnect Validator.
“Ensuring that on-chip interconnects perform optimally is a baseline requirement for today’s complex SoCs, system designers need the cycle-accurate analysis that Interconnect Workbench provides to make trade-offs and enhance their designs,” said Andy Nightingale, director, System IP Products, Processor Division at ARM.
“Interconnect Workbench is specifically targeted at addressing the complexity of today’s SoCs,” said Ziv Binyamini, corporate Vice President of System and Verification Solutions, System and Verification Group at Cadence.
“In addition to optimising performance of their ARM-based mobile, consumer, networking and storage SoCs, users can also get their designs to market much faster.”
Cadence
